Scott Mueller's Upgrading and Repairing PCs Forum

Scott,

On a server, such as an HP DL360, if there are multiple CPUs (of the same make and speed) but with different steppings and revisions, does the CPU with the lower stepping usually go in slot 0 or in slot 1?

I'm the proud new owner of a used DL360 with multiple CPUs with different steppings and revisions and I want to make sure that they are placed properly.

The HP documentation is silent on the issue, but I've read various chatter here and there about which is correct but there is disagreement.

I know that IBM eServer xSeries boxes *are* picky about this.

Thanks,
Ed

The only universal rule I know is that all CPUs in a DP (Dual Processor) configuration should be exactly the same revision and stepping. For example, in the Intel D5400XS motherboard manual, it specifically states in section 1.4 that "Processors installed must be identical as determined by identical sSpec numbers.": http://download.intel.com/support/mothe ... 8001us.pdf

If your server docs don't specifically state what is or isn't supported, then you'll need to consult the processor docs, which are often fairly specific about mixing and matching DP capable CPUs. Intel has a general reference on the subject here:

How Do I Know Which Processors Support Dual Processing?
http://developer.intel.com/support/proc ... 007878.htm

If you read this carefully, you'll see that they basically state that mixing steppings is generally OK, however mixing speeds or other attributes is not. There are exceptions though, such that unless you have a reference that states a mix is OK, the only sure thing is if even the steppings are the same. You didn't say which type of processor your server supports, but for example the Xeon 5400 series datasheet http://download.intel.com/design/xeon/d ... 318589.pdf states (in section 2.11 - Mixing Processors):

"Intel supports and validates dual processor configurations only in which both processors operate with the same FSB frequency, core frequency, power segments, and have the same internal cache sizes. Mixing components operating at different internal clock frequencies is not supported and will not be validated by Intel. Combining processors from different power segments is also not supported..."

"...Mixing processors of different steppings but the same model (as per CPUID instruction) is supported..."

So I guess for *that* CPU, you can get away with mixing different steppings.

Bottom line: Unless your server or processor documentation specifically states otherwise, I recommend using chips with the same revision and stepping in DP (Dual Processor) configurations, however the mixing of different steppings is supported in many cases. In cases where steppings are mixed, I don't know of any rule about which should be placed where, but I'd probably go with the lower (earlier) stepping in the first socket as a common sense rule of thumb. Let me know if you find any official word more specific to your server and processors that might give a more precise answer. Scott.

Scott,

Thank you for your comprehensive reply. I'll check for my specific processor and if I see any info there clarifies the situation. I'll post any relevant info that I find. At first glance, however, it looks like my processors may be ok - probably in the right slots (the lower stepping is in slot 0).

Ed

Scott,

The processors in question are Xeon 3.06 GHz 533 MHz FSB, 512 Mb L2, eSpec SL6VP.

From http://download.intel.com/design/Xeon/d ... 213506.pdf , section 2.5.1, "Mixing Processors":

"Intel only supports those processor combinations operating with the same front side bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update. Additional details are provided in AP-485, the Intel Processor Identification and the CPUID Instruction application note."

Searching the rest of this document and the other documents referenced, there is no specific mention about which stepping goes in which CPU slot. I would assume that if there was an issue or concern with placement, Intel would have posted prominent warnings or advisories.

I'm going to therefore assume that all is well.

Thanks,
Ed