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Scott Mueller's Upgrading and Repairing PCs Forum • View topic - Multiple Physical CPUs with Different Steppings, Revs
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 Post subject: Multiple Physical CPUs with Different Steppings, Revs
 Post Posted: Wed Nov 26, 2008 9:17 pm 
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Posts: 64
Location: Port Orchard, WA
Scott,

On a server, such as an HP DL360, if there are multiple CPUs (of the same make and speed) but with different steppings and revisions, does the CPU with the lower stepping usually go in slot 0 or in slot 1?

I'm the proud new owner of a used DL360 with multiple CPUs with different steppings and revisions and I want to make sure that they are placed properly.

The HP documentation is silent on the issue, but I've read various chatter here and there about which is correct but there is disagreement.

I know that IBM eServer xSeries boxes *are* picky about this.

Thanks,
Ed


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 Post subject: Re: Multiple Physical CPUs with Different Steppings, Revs
 Post Posted: Wed Nov 26, 2008 10:18 pm 
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 Post subject: Re: Multiple Physical CPUs with Different Steppings, Revs
 Post Posted: Wed Nov 26, 2008 10:58 pm 
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Scott,

Thank you for your comprehensive reply. I'll check for my specific processor and if I see any info there clarifies the situation. I'll post any relevant info that I find. At first glance, however, it looks like my processors may be ok - probably in the right slots (the lower stepping is in slot 0).

Ed


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 Post subject: Re: Multiple Physical CPUs with Different Steppings, Revs
 Post Posted: Fri Nov 28, 2008 2:36 pm 
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Scott,

The processors in question are Xeon 3.06 GHz 533 MHz FSB, 512 Mb L2, eSpec SL6VP.

From http://download.intel.com/design/Xeon/d ... 213506.pdf , section 2.5.1, "Mixing Processors":

"Intel only supports those processor combinations operating with the same front side bus frequency, core frequency, VID settings, and cache sizes. Not all operating systems can support multiple processors with mixed frequencies. Intel does not support or validate operation of processors with different cache sizes. Mixing processors of different steppings but the same model (as per CPUID instruction) is supported, and is outlined in the Intel® Xeon™ Processor Specification Update. Additional details are provided in AP-485, the Intel Processor Identification and the CPUID Instruction application note."

Searching the rest of this document and the other documents referenced, there is no specific mention about which stepping goes in which CPU slot. I would assume that if there was an issue or concern with placement, Intel would have posted prominent warnings or advisories.

I'm going to therefore assume that all is well.

Thanks,
Ed


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